The present invention relates to the manufacturing of semiconductor devices, and more particularly, to laser anneal processes having improved efficiency.
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS semiconductor device includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS transistor is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant performance increases, for example, from decreasing performance degrading resistances and parasitic capacitances. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOSFET structures.
As the distance between the source region and the drain region of the MOSFET (i.e., the physical channel length) decreases, in the effort to increase circuit speed and complexity, the junction depth of source/drain regions must also be reduced to prevent unwanted source/drain-to-substrate junction capacitance. However, obtaining these smaller junction depths tests the capabilities of current processing techniques, such as ion implantation with activation annealing using rapid thermal annealing. Rapid thermal annealing typically involves heating the silicon wafer, after implanting, under high-intensity heat lamps. Implanting or doping amorphitizes the silicon substrate, and the activation annealing is used to recrystallize the amorphitized silicon region.
As a result of the limitations of rapid thermal annealing, laser thermal annealing is being implemented, particularly for ultra-shallow junction depths. Laser thermal annealing may be performed after ion implantation of a dopant and involves heating the doped area with a laser. The laser radiation rapidly heats the exposed silicon such that the silicon begins to melt. The diffusivity of dopants into molten silicon is about eight orders of magnitude higher than in solid silicon. Thus, the dopants distribute almost uniformly in the molten silicon and the diffusion stops almost exactly at the liquid/solid interface. The heating of the silicon is followed by a rapid quench to solidify the silicon, and this process allows for non-equilibrium dopant activation in which the concentration of dopants within the silicon is above the solid solubility limit of silicon. Advantageously, this process allows for ultra-shallow source/drain regions that have an electrical resistance about one-tenth the resistance obtainable by conventional rapid thermal annealing.
A problem associated with laser thermal annealing is that the fluence absorbed by the substrate can vary across the wafer, as illustrated in FIG. 1. For example, as the density of gate electrodes 4 in a particular area of a wafer 2 increases, the amount of fluence 6 reflected or scattered from that particular area also increases, as compared to an area with a lesser density of gate electrodes 4. When the fluence 6 reflected by a particular area increases, the amount of fluence 7 absorbed by that area decreases. The opposite holds true as the density of gate electrodes 4 in a particular area decreases. Therefore, depending upon certain factors, such as the density of gate electrodes, the amount of fluence 7 absorbed at given areas varies throughout the wafer 2.
As an illustrative example, a first region 8 and a second region 9 are positioned on a semiconductor wafer 2, and both the first and second regions 8, 9 are assumed to have identical requirements for fluence 7 absorbed during laser thermal annealing. The density of gate electrodes 4 in the first region 8 is also assumed to be higher than the density of gate electrodes 4 in the second region 9, and the first region 8 reflects approximately 10% of the laser energy 6 during laser thermal annealing, and the second region 9 reflects approximately 1% of the laser energy 6 during laser thermal annealing. Thus, the second region 9 absorbs about 10% more fluence 7 than the first region 8. As both the first and second regions 8, 9 have the same fluence requirements, either the first region 8 receives too little fluence 7 or the second region 9 receives too much fluence 7 or both. Accordingly, a need exists for an improved laser anneal process that allows a greater control of fluence being provided to the substrate at different areas on the substrate.
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device that allows for control of the fluence absorbed by different portions on a semiconductor wafer. The method includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by the portion, if the portion was not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.
By providing one or more tuning layers, the fluence received in particular portions on the wafer during laser thermal annealing can be controlled. Thus, when an area on the substrate receives too much or too little fluence, the fluence received by that particular portion can be adjusted to a more optimal amount using the tuning layer. Furthermore, if the wafer includes portions which require differing amounts of fluence absorption, the tuning layer can be used to modify the fluence absorption of these portions without requiring the modification of the fluence provided by the laser.
In another aspect of the invention, the ions are introduced into the substrate before the formation of the tuning layer, or alternatively, the ions are introduced into the substrate after initiation of the tuning layer formation step. Also, the tuning layer can be formed from such materials as a resist, an organic anti-reflective material, or a dielectric.
One method of forming the tuning layer includes forming a first layer of tuning material over the substrate, and removing portions of the first layer to form the tuning layer. This method can also include forming a second layer of the tuning material over the substrate and the first layer. Another method of forming the tuning layer includes forming a first layer of a first tuning material over the substrate, removing portions of the first layer, and forming a second layer of a second tuning material over the first layer and the substrate to form the tuning layer. This method can also include planarizing the first and second layers such that the first and second layers have approximately equal depths. Still another method of forming the tuning layer includes forming a first layer of adjustable tuning material over the substrate, and selectively irradiating portions of the first layer to adjust the properties of the tuning material or selectively doping portions of the first layer to adjust the properties of the tuning material.
In another embodiment of the invention, the method includes forming semiconductor features over a substrate, forming a tuning layer over at least a portion of the substrate, and laser thermal annealing. The tuning layer adjusts the amount of fluence absorbed during the step of laser thermal annealing by causing an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by the portion, if the portion was not covered by the tuning layer. The substrate has a first region and a second region with the density of the semiconductor features in the first region different than the density of the semiconductor features in the second region.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.